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RIS citation export for THCPR03: A Safety Rated FPGA Framework for Fast Safety Systems

AU  - Tao, F.
AU  - Bennett, B.M.
AU  - Brown, D.G.
AU  - Jones, J.
AU  - Stettler, M.W.
ED  - White, Karen S.
ED  - Brown, Kevin A.
ED  - Dyer, Philip S.
ED  - Schaa, Volker RW
TI  - A Safety Rated FPGA Framework for Fast Safety Systems
J2  - Proc. of ICALEPCS2019, New York, NY, USA, 05-11 October 2019
CY  - New York, NY, USA
T2  - International Conference on Accelerator and Large Experimental Physics Control Systems
T3  - 17
LA  - english
AB  - In this paper, we will introduce a generic safety-rated FPGA design template. FMEDA analysis, hardware reliability modeling, firmware development, verification and validation will be described in details to demonstrate the IEC 61508 compliant development process. In this dual redundant design, each chain consists a FPGA chip from different manufacturers to minimize the potential common cause failures. Cross checks between FPGAs and end-to-end self-checks are performed to increase the diagnostic coverage and improve the reliability. Based on this safety FPGA template, an Average Current Monitor (ACM) system is developed at SLAC with the addition of a safety PLC for diagnostics and a HMI for user interface. The overall system is deployed as part of Beam Containment System (BCS) to limit the beam current with the target Safety Integrity Level (SIL) 2.
PB  - JACoW Publishing
CP  - Geneva, Switzerland
SP  - 1626
EP  - 1629
KW  - electron
KW  - hardware
KW  - diagnostics
DA  - 2020/08
PY  - 2020
SN  - 2226-0358
SN  - 978-3-95450-209-7
DO  - doi:10.18429/JACoW-ICALEPCS2019-THCPR03
UR  - https://jacow.org/icalepcs2019/papers/thcpr03.pdf
ER  -