Author: Paiagua, S.
Paper Title Page
TUAPP01 Hardware-in-the-Loop Testing of Accelerator Firmware 659
  • C. Serrano, M. Betz, L.R. Doolittle, S. Paiagua, V.K. Vytla
    LBNL, Berkeley, California, USA
  Continuous Integration (CI) is widely used in industry, especially in the software world. Here we propose a combination of CI processes to run firmware and software tests both in simulation and on real hardware that can be well adapted to FPGA-based accelerator electronics designs. We have built a test rack with a variety of hardware platforms. Relying on source code version control tools, when a developer submits a change to the code base, a multi-stage test pipeline is triggered. Unit tests are run automatically, bitstreams are generated for the various supported FPGA platforms and loaded onto the FPGAs in the rack, and tests are run on hardware. Reports are generated upon test completion and notifications are sent to the developers in case of failure.  
slides icon Slides TUAPP01 [9.740 MB]  
DOI • reference for this paper ※  
About • paper received ※ 07 October 2019       paper accepted ※ 20 October 2019       issue date ※ 30 August 2020  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)