Hardware Technology
Paper Title Page
MOMPR005 Development of a New Data Acquisition System for a Photon Counting Detector Prototype at SOLEIL Synchrotron 162
MOPHA144   use link to see paper's listing under its alternate paper code  
 
  • G. Thibaux, Y.-M. Abiven, D. Bachiller-Perea, J. Bisou, A. Dawiec, A. Jarnac, B. Kanoute, F. Langlois, C. Laulhé, C. Menneglier, A. Noureddine, F. Orsini, Y. Sergent
    SOLEIL, Gif-sur-Yvette, France
  • P. Grybos, A. Koziol, P. Maj
    AGH University of Science and Technology, Kraków, Poland
  • C. Laulhe
    Université Paris-Saclay, Saint-Aubin, France
 
  Time-resolved pump-probe experiments at SOLEIL Synchrotron (France) have motivated the development of a new and fast photon counting camera prototype. The core of the camera is a hybrid pixel detector, based on the UFXC32k readout chips bump-bonded to a silicon sensor. This detector exhibits promising performances with very fast readout time, high dynamic range, extended count rate linearity and optimized X-ray detection in the energy range 5-15 keV. In close collaboration with CRISTAL beamline, SOLEIL’s Detector, Electronics and Software Groups carried out a common R&D project to design and realize a 2-chips camera prototype with a high-speed data acquisition system. The system has been fully integrated into Tango and Lima data acquisition framework used at SOLEIL. The development and first experimental results will be presented in this paper.  
poster icon Poster MOMPR005 [1.832 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOMPR005  
About • paper received ※ 30 September 2019       paper accepted ※ 10 October 2019       issue date ※ 30 August 2020  
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MOPHA023 Applications of an EPICS Embedded and Credit-card Sized Waveform Acquisition 242
 
  • Y.-S. Cheng, K.T. Hsu, K.H. Hu, D. Lee, C.Y. Liao, C.Y. Wu
    NSRRC, Hsinchu, Taiwan
 
  To eliminate long distance cabling for improving signal quality, the remote waveform access supports have been developed for the TPS (Taiwan Photon Source) and TLS (Taiwan Light Source) control systems for routine operation. The previous mechanism was that a dedicated EPICS IOC has been used to communicate with the present Ethernet-based oscilloscopes to acquire each waveform data. To obtain higher reliability operation and low power consumption, the FPGA and SoC (System-on-Chip) based waveform acquisition which embedded an EPICS IOC has been adopted to capture the waveform signals and process to the EPICS PVs (Process Variables). According to specific purposes use, the different graphical applications have been designed and integrated into the existing operation interfaces. These are convenient to observe waveform status and to analyse the caught data on the control consoles. The efforts are described at this paper.  
poster icon Poster MOPHA023 [5.076 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA023  
About • paper received ※ 30 September 2019       paper accepted ※ 08 October 2019       issue date ※ 30 August 2020  
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MOPHA052 Evolution Based on MicroTCA and MRF Timing System 334
 
  • F. Gougnaud, P. Bargueden, J.F. Denis, A. Gaget, P. Guiho, T.J. Joannem, A. Lotode, Y. Lussignol, Y. Mariette, V. Nadot, N. Solenne
    CEA-DRF-IRFU, France
  • Q. Bertrand, G. Ferrand, F. Gohier
    CEA-IRFU, Gif-sur-Yvette, France
  • I. Hoffman Moran, E. Reinfeld, I. Shmuely
    Soreq NRC, Yavne, Israel
 
  For many years our Institute CEA IRFU has had a sound experience in VME and EPICS. For the accelerator projects SPIRAL2 at Ganil in Normandy and IFMIF/LIPAc at JAEA/Rokkasho (Japan) the EPICS control systems were based on VME. For 5 years our Institute has been involved in several in-kind collaboration contracts with ESS. For the first contracts (ESS test stands, Source and LEBT controls) ESS recommended us to use VME based solutions on IOxOS boards. Our close collaboration with ESS, their support and the requirements for new projects have led us to develop a standardized hardware and software platform called IRFU EPICS Environment based on microTCA.4 and MRF timing system. This paper describes the advantages of the combination of these recent technologies and the local control system architectures in progress for the SARAF project.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA052  
About • paper received ※ 30 September 2019       paper accepted ※ 11 October 2019       issue date ※ 30 August 2020  
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MOPHA124 Local Oscillator Rear Transition Module for 704.42 MHz LLRF Control System at ESS 516
 
  • I. Rutkowski, K. Czuba, M.G. Grzegrzółka
    Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
 
  Funding: Work supported by Polish Ministry of Science and Higher Education, decision number DIR/WK/2016/03.
This paper describes the specifications, architecture, and measurements’ results of the MTCA-compliant Local Oscillator (LO) Rear Transition Module (RTM) board providing low phase noise clock and heterodyne signals for the 704.42 MHz Low Level Radio Frequency (LLRF) control system at the European Spallation Source (ESS). The clock generation and LO synthesis circuits are based on the module presented at ICALEPCS 2017. The conditioning circuits for the input and output signals must simultaneously achieve the desired impedance matching, spectral purity, output power as well as the phase noise requirements. The reference conditioning circuit presents an additional challenge due to input power range being significantly wider than the output range. The circuits monitoring the power levels of critical signals and voltages of supply rails for remote diagnostics as well as the programmable logic devices used to set the operating parameters via Zone3 connector are described.
 
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA124  
About • paper received ※ 04 October 2019       paper accepted ※ 10 October 2019       issue date ※ 30 August 2020  
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MOPHA153 SoC Technology for Embedded Control and Interlocking Within Fast Pulsed Systems at CERN 592
 
  • P. Van Trappen, E. Carlier, M. Gauthier, N. Magnin, E.J. Oltedal, J. Schipper
    CERN, Geneva, Switzerland
 
  The control of pulsed systems at CERN requires often the use of fast digital electronics to perform tight timing control and fast protection of high-voltage pulsed generators. For the implementation of such functionalities, a FPGA is the perfect candidate for the digital logic, however with limited integration potential within the control system. The market push for integrated devices, so called System on a Chip (SoC) - a tightly coupled ARM processing system and specific programmable logic in a single device, has allowed a better integration of the various components required for the control of pulsed systems. This technology is used for the implementation of fast switch interlocking logic, integrated within the CERN control framework by using embedded Linux running a Snap7 server. It is also used for the implementation of a lower-tier communication bridge between a front-end computer and a high fan-out multiplexing programmable logic for timing and analogue low-level control. This paper presents these two projects where the SoC technology has been deployed and discusses possible further applications within distributed real-time control architecture for distributed pulsed systems.  
poster icon Poster MOPHA153 [0.828 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA153  
About • paper received ※ 30 September 2019       paper accepted ※ 10 October 2019       issue date ※ 30 August 2020  
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TUAPP01 Hardware-in-the-Loop Testing of Accelerator Firmware 659
 
  • C. Serrano, M. Betz, L.R. Doolittle, S. Paiagua, V.K. Vytla
    LBNL, Berkeley, California, USA
 
  Continuous Integration (CI) is widely used in industry, especially in the software world. Here we propose a combination of CI processes to run firmware and software tests both in simulation and on real hardware that can be well adapted to FPGA-based accelerator electronics designs. We have built a test rack with a variety of hardware platforms. Relying on source code version control tools, when a developer submits a change to the code base, a multi-stage test pipeline is triggered. Unit tests are run automatically, bitstreams are generated for the various supported FPGA platforms and loaded onto the FPGAs in the rack, and tests are run on hardware. Reports are generated upon test completion and notifications are sent to the developers in case of failure.  
slides icon Slides TUAPP01 [9.740 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP01  
About • paper received ※ 07 October 2019       paper accepted ※ 20 October 2019       issue date ※ 30 August 2020  
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TUAPP02 Development of the MTCA.4 I/O Cards for SPring-8 Upgrade and New 3 GeV Light Source 665
 
  • T. Fukui, N. Hosoda
    RIKEN SPring-8 Center, Innovative Light Sources Division, Hyogo, Japan
  • M. Ishii
    JASRI/SPring-8, Hyogo-ken, Japan
  • E. Iwai, H. Maesaka, T. Ohshima
    RIKEN SPring-8 Center, Sayo-cho, Sayo-gun, Hyogo, Japan
 
  We will start a full energy injection from the SACLA to the SPring-8 from next year as a part of the SPring-8 upgrade. For this, we developed several I/O cards with the MTCA.4 form factor. One of the key issues is a timing synchronization between SACLA and SPring-8. We implemented required functions on the FPGA logic of a commercially available I/O card. We develop a module to distribute a trigger and clocks. We also developed cards used for the beam position monitor (BPM) and low-level RF system (LLRF). Those are included two types of cards. One is a 16-bit digitizer used for LLRF for the SPring-8 since 2018 march. We will use the card for the BPM with modified FPGA logic. Second is an implementation of functions with the pulsed RF signals processed on the FPGA logic of a commercially available card. These functions are used for the BPM of the beam transport line from the SACLA to SPring-8. The existing system is used 1 Hz beam repetition but we need more than 10 Hz to achieve an injection time less than 20 minutes to maximize user time. We will report the performance of the MTCA.4 cards, the upgrade plan of the SPring-8, and the construction of the 3 GeV Light Source.  
slides icon Slides TUAPP02 [7.123 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP02  
About • paper received ※ 01 October 2019       paper accepted ※ 20 October 2019       issue date ※ 30 August 2020  
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TUAPP03 Low-Cost Modular Platform for Custom Electronics in Radiation-Exposed and Radiation-Free Areas at CERN 671
 
  • G. Daniluk, C. Gentsos, E. Gousiou, L. Patnaik, M. Rizzi
    CERN, Geneva, Switzerland
 
  The CERN control system is comprised of multiple layers of hardware and software. These tiers extend from the hardware deployed close to the machine, up to the software running on computers that operators use for control and monitoring. We are currently developing a new centrally supported service in the layers closest to the accelerator - Distributed I/O and Fieldbus. A key aspect of this project is the selection of industrial standards for the layers, which are currently dominated by custom, in-house designed solutions. Regarding the Distributed I/O layer, this paper describes how we are adapting CompactPCI Serial (CPCI-S) to be suitable as the low-cost modular hardware platform for remote analog and digital I/O applications in radiation-exposed as well as radiation-free areas. We are designing a low cost 3U chassis with a CPCI-S backplane accompanied by a radiation tolerant, switched-mode power supply and an FPGA-based System Board. Regarding the Fieldbus layer, the paper focuses on the radiation-tolerant implementation of the Industrial Ethernet protocol, Powerlink.  
slides icon Slides TUAPP03 [7.663 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP03  
About • paper received ※ 27 September 2019       paper accepted ※ 10 October 2019       issue date ※ 30 August 2020  
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TUAPP04 Extending the Life of the VME Infrastructure at BNL 678
 
  • W.E. Pekrul, C. Theisen
    BNL, Upton, New York, USA
 
  A large installation of VME controllers have been used to control and monitor the RHIC Accelerator complex at BNL. As this equipment ages a number of upgrade options are being pursued. This paper describes an FPGA based VME controller board development being undertaken to provide a upgrade path for control applications that reuses existing racks and power supplies and a catalogue of custom application boards. This board is based on a Xilinx Zynq that includes an ARM-9 and a large FPGA fabric. The board includes DRAM, SPI-Flash, Ethernet, SD card, USB, SFP, FMC and an Artix FPGA to support the VME bus protocol. The first application of a magnet quench detector will also be described.  
slides icon Slides TUAPP04 [2.138 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP04  
About • paper received ※ 01 October 2019       paper accepted ※ 20 October 2019       issue date ※ 30 August 2020  
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TUAPP05 PandABlocks - a Flexible Framework for Zynq7000-Based SoC Configuration 682
 
  • G.B. Christian, M.G. Abbott, T.M. Cobb, C.A. Colborne, A.M. Cousins, P. Garrick, T.E. Trafford, I.S. Uzun
    DLS, Oxfordshire, United Kingdom
  • Y.-M. Abiven, J. Bisou, F. Langlois, G. Renaud, G. Thibaux, S. Zhang
    SOLEIL, Gif-sur-Yvette, France
  • S.M. Minolli
    NEXEYA Systems, La Couronne, France
 
  The PandABlocks framework comprises the FPGA logic, TCP server, webserver, boot sources and root filesystem, developed for the PandABox platform by Diamond Light Source and Synchrotron Soleil, for advanced beamline scanning applications. The PandABox platform uses a PicoZed System-on-Module, comprising a Zynq-7030 SoC, coupled to a carrier board containing removable position encoder modules, as well as various input and outputs. An FMC connector provides access to ADC/DACs or additional I/O, and gigabit transceivers on the Zynq allow communication with other systems via SFP modules. Specific functions and hardware resources are represented by functional blocks, which are run-time configurable and re-wireable courtesy of multiplexed data and control buses shared between all blocks. Recent changes to the PandABlocks framework are discussed which allow the auto-generation of the FPGA code and tcl automation scripts, using Python and the jinja2 templating engine, for any combination of functional blocks and SFP/FMC modules. The framework can target hardware platforms other than PandABox and could be deployed for other Zynq-based applications requiring on-the-fly reconfigurable logic.  
slides icon Slides TUAPP05 [5.484 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP05  
About • paper received ※ 30 September 2019       paper accepted ※ 10 October 2019       issue date ※ 30 August 2020  
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WEPHA016 A/D and D/A Processing Unit for Real Time Control of Suspended Masses in Advanced Virgo Interferometer 1098
 
  • M. Bitossi, A. Gennai
    INFN-Pisa, Pisa, Italy
  • D. Passuello
    University of Pisa and INFN, Pisa, Italy
 
  AdV* is the project to upgrade** the VIRGO*** interferometric detector of gravitational waves. We present a major upgrade consisting of the design of new control electronics of the seismic isolation systems called Super-Attenuators (SAs)*. SAs are mechanical structures used to insulate optical elements from seismic noise. The control electronics are used to manage sensors, actuators, and stepping motors placed in the SAs. The design effort resulted in a high-performance signal conditioning and processing platform (UDSPT) that enables users to implement hard real-time control systems. The form factor is a variation of a double compact Module PICMG AMC.0 R2.0 Advanced MC. The key features are a TI DSP embedded, two GE ports, an AMC Interface containing SRIO, and GE, an FPGA interfacing data converters through PCIe. Additionally, it includes six 24-bit 3.83 MHz ADC and six 24-bit 320 kHz DAC converters, with fully differential inputs and outputs. In a single local control unit - a single 6U x 19 crate - up to 72 ADC + 72 DAC channels supported by 720 GFLOPs are allocated. A total of 20 local control units have been installed and currently are controlling ten SAs in the AdV detector.
*AdV Tech Des Rep 13 April 2012.
**Advanced Virgo Baseline Design
***J. Phys.: Conf. Ser., 203(2010)012074.
 
poster icon Poster WEPHA016 [1.858 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA016  
About • paper received ※ 23 September 2019       paper accepted ※ 11 October 2019       issue date ※ 30 August 2020  
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WEPHA023 Co-Simulation of HDL Using Python and MATLAB Over Tcl TCP/IP Socket in Xilinx Vivado and Modelsim Tools 1127
 
  • Ł. Butkowski, B. Dursun, Ç. Gümüş, M.K. Karakurt
    DESY, Hamburg, Germany
 
  This paper presents the solution, which helps in the simulation and verification of the implementation of the Digital Signal Processing (DSP) algorithms written in hardware description language (HDL). Many vendor tools such as Xilinx ISE/Vivado or Mentor Graphics ModelSim are using Tcl as an application programming interface. The main idea of the co-simulation is to use the Tcl TCP/IP socket, which is Tcl build in feature, as the interface to the simulation tool. Over this interface the simulation is driven by the external tool. The stimulus vectors as well as the model and verification are implemented in Python or MATLAB and the data with simulator is exchanged over dedicated protocol. The tool, which was called cosimtcp, was developed in Deutsches Elektronen-Synchrotron (DESY). The tool is a set of scripts that provide a set of functions. This tool has been successfully used to verify many DSP algorithms implemented in the FPGA chips of the Low Level Radio Frequency (LLRF) and synchronization systems of the European X-Ray Free Electron Laser (E-XFEL) accelerator. Cosimtcp is an open source available tool.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA023  
About • paper received ※ 30 September 2019       paper accepted ※ 19 October 2019       issue date ※ 30 August 2020  
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WEPHA028 Power Supply Controller for Future Accelerator Facilities at BINP 1145
 
  • P.B. Cheblakov, A.V. Gerasev, S.E. Karnaev, D.V. Senkov
    BINP SB RAS, Novosibirsk, Russia
 
  A design of a new power supply controller was initiated in BINP for upgrade of existing accelerator facilities and for demands of future projects. Any accelerator facility includes a set of diverse power supplies which controllers have different specifications: number and precision of DAC/ADC channels, speed and algorithm of operation. Therefore, the main idea is to elaborate a controller, which consists of common digital part including an interface with a control system and specialized analog frontend that fits to power supplies requirements. The digital part provides easy integration to control system by means of some standard network protocol and performing some data processing and analysis. Ethernet is used for communication with controllers, MQTT is under consideration as a high-level transport protocol in some cases and EPICS IOC was tested to be embedded into controller. The initial prototype of controller is developed and deployed at VEPP-3 storage ring. The status of the work and future plans are presented in the paper.  
poster icon Poster WEPHA028 [9.746 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA028  
About • paper received ※ 04 October 2019       paper accepted ※ 20 October 2019       issue date ※ 30 August 2020  
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WEPHA120 Management of MicroTCA Systems and its Components with a DOOCS-Based Control System 1372
 
  • V. Petrosyan, K. Rehlich, E. Sombrowski
    DESY, Hamburg, Germany
 
  An extensive management functionality is one of the key advantages of the MicroTCA.4 standard. Monitoring and control of more than 350 MicroTCA crates and thousands of AMC and RTM modules installed at XFEL, FLASH, SINBAD and ANGUS experiments has been integrated into the DOOCS-based control system. A DOOCS middle layer server together with Java-based GUIs - JDDD and JDTool - developed at DESY, enable remote management and provide information about MicroTCA shelves and components. The integrated management includes inventory information, monitoring current consumption, temperatures, voltages and various types of the built-in sensors. The system event logs and collected histories of the sensors are used to investigate failures and issues.  
poster icon Poster WEPHA120 [1.612 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA120  
About • paper received ※ 24 September 2019       paper accepted ※ 10 October 2019       issue date ※ 30 August 2020  
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WESH3002 Control System for Fast Components of Electron Beam Welding Machines 1516
WEPHA053   use link to see paper's listing under its alternate paper code  
 
  • A.V. Gerasev, P.B. Cheblakov
    BINP SB RAS, Novosibirsk, Russia
 
  Modern electron beam machines for different applications including welding, additive technologies and etc. consist of many different subsystems, which should be controlled and monitored. They could be divided by so-called fast and slow subsystems. Slow subsystems allow reaction time to be around couple of seconds that can be implemented using PC. Fast subsystems require time to be around hundreds of microseconds combined with flexible logic. We present an implementation of such fast system for mechanical moving platform and electron beam control. The core of this system is single board computer Raspberry Pi. We employed a technique of fast waveform generation using Raspberry Pi on-chip DMA to manipulate stepper motors. Raspberry Pi was equipped by external CAN controller to operate an electron beam via CAN DACs. Special software was developed including libraries for low- and high-level technical process control written in C and Rust; and in-browser graphical user interface over HTTP and WebSockets. Finally, we assembled our hardware inside standard 19-inch rack mount chassis and integrated our system inside experimental electron beam machine infrastructure.  
poster icon Poster WESH3002 [6.479 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WESH3002  
About • paper received ※ 02 October 2019       paper accepted ※ 09 October 2019       issue date ※ 30 August 2020  
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